• 专利附录
  • 专利说明
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    • 专利摘要:
    Disclosed are a method of controlling a split screen output of an image reproducing apparatus for simultaneously outputting to two screens while reducing the distortion of the aspect ratio when the split screen is output from the image reproducing apparatus. Channel 1 is selected from a plurality of analog broadcast signals input from the antenna, and the synchronization signal of the channel 1 is separated to generate a clock 1 and a clock 3 having a different frequency from the clock 1, and digitally outputs the broadcast signal of the channel 1. It is converted to and stored as corresponding to clock 1. The channel 2 is selected from the plurality of analog broadcast signals, the synchronization signal of the channel 2 is separated, and the clock 2 is generated, and the broadcast signal of the channel 2 is converted into digital and stored corresponding to the clock 2. The stored digital signals according to the channel 1 and the channel 2 are read out to correspond to the clock 3 and restored. The digital signals according to the restored channel 1 and channel 2 are sequentially output with a certain time difference. Only digital signals corresponding to a specific portion of the digital signals corresponding to channel 1 are selected, and only digital signals corresponding to a specific portion of the digital signals corresponding to channel 2 are selected and mixed into one image signal. The mixed video signal is converted into an analog signal, and a sync signal is generated to output a corresponding sync signal.
    公开号:KR19980054828A
    申请号:KR1019960074013
    申请日:1996-12-27
    公开日:1998-09-25
    发明作者:나대희；이기순
    申请人:배순훈；대우전자 주식회사；
    IPC主号:
    专利说明:

    Method for controlling split screen output of an image reproducing apparatus and apparatus for performing the same
    The present invention relates to a method for controlling split screen output of an image reproducing apparatus and an apparatus for performing the same. Particularly, the image reproducing apparatus simultaneously outputs to two screens while reducing the distortion of aspect ratio during split screen output. The present invention relates to a split screen output control method of an image reproducing apparatus and an apparatus for performing the same.
    In general, the picture-in-picture (PIP) function divides one screen of an image reproducing apparatus and outputs multiple channels simultaneously on one screen.
    FIG. 1 is a schematic diagram illustrating that a screen distortion phenomenon occurs in a split screen output function in a general image reproducing apparatus, and FIG. 2 is a waveform diagram illustrating a split screen output operation in a general image reproducing apparatus.
    As shown in FIG. 1, the PIP function of outputting a plurality of different screens according to a broadcasting channel on one screen divides the screen of the video reproducing apparatus horizontally or vertically, and the image signal received from each channel for each divided screen. Outputs simultaneously.
    In order to perform the PIP function in the image reproducing apparatus, as shown in FIG. 2, a plurality of tuners included in the image reproducing apparatus receives an image signal input in analog form according to a synchronization signal (Sync signal). That is, as shown in (a) of FIG. 2, when an analog video signal corresponding to an arbitrary channel 1 is input from one tuner, as shown in (b) of FIG. 2, the arbitrary channel 2 is different from another tuner. An analog video signal corresponding to is input. The analog signals inputted from the tuners are digitally converted by sampling (coding) according to the screen division mode. The image signal converted to digital should compress the amount of image data to correspond to the size of the divided screen. That is, the digitally converted image data is compressed and stored in a memory using a write clock according to a screen division mode (horizontal division or vertical division). That is, in the case where the screen is divided into two and the arbitrary channel 1 and the channel 2 are simultaneously output to the divided screen, the analog video signal corresponding to the channel 1 is 1/2 as shown in FIG. Is compressed. The analog video signal corresponding to channel 2 is also compressed to 1/2, as shown in FIG.
    In conclusion, as shown in (e) of FIG. 2, the video signal input in channel 1 and the video signal input in channel 2 are compressed between the synchronization signal and the next synchronization signal. As described above, when the compressed screen reads data compressed and stored in the memory at a normal read clock, the divided screen is simultaneously output.
    In the conventional video reproducing apparatus, the split screen output method uses a method of converting an image signal into digital, compressing the converted digital signal, and storing the converted digital signal in a memory. Therefore, there is a problem in that the screen is distorted when the aspect ratio, which is the ratio of the width to height of each frame of the image signal, is changed during compression storage in the memory.
    The present invention was devised to solve the above problems, and a first object of the present invention is to divide a central portion of a screen without compressing a video signal input from each channel when outputting a split screen in a video reproducing apparatus. The present invention provides a method for controlling split screen output of an image reproducing apparatus that can be output on a screen and vary the amount of output data.
    In addition, a second object of the present invention is to provide an apparatus suitable for performing the split screen output control method.
    1 is a schematic diagram illustrating a split screen output function in a general image reproducing apparatus.
    2 is a waveform diagram illustrating a split screen output process in a general image reproducing apparatus.
    3 is a block diagram illustrating an apparatus for controlling split screen output of an image reproducing apparatus according to an exemplary embodiment.
    4A to 4D are schematic diagrams illustrating a split screen output from a split screen output control apparatus of an image reproducing apparatus according to each embodiment of the present invention.
    5A to 5I are waveform diagrams for describing a split screen output process in the split screen output control apparatus of the image reproducing apparatus according to the first embodiment of the present invention.
    6A to 6F are waveform diagrams for describing an operation of the line memory in the split screen output control apparatus of the image reproducing apparatus according to the second embodiment of the present invention.
    7A to 7F are waveform diagrams for explaining the operation of the line memory in the split screen output control apparatus of the image reproducing apparatus according to the third embodiment of the present invention.
    Explanation of symbols for the main parts of the drawings
    100a, 100b: antenna 102a, 102b: tuner
    104a, 104b: Sync signal separator 106a, 106b: PLL circuit
    108a, 108b: A / D converter 110a, 110b: line memory
    112a, 112b: line memory 114: MUX
    116: D / A converter 116: mixing device
    120: controller
    In a split screen output control method of an image reproducing apparatus according to an embodiment of the present invention for performing the first object, channel 1 is selected from a plurality of analog broadcast signals input from an antenna, and a synchronization signal of channel 1 is selected. Generating a clock 1 and a clock 3 having a different frequency from the clock 1, converting the broadcast signal of the channel 1 into digital, and storing the clock signal corresponding to the clock 1;
    Selecting a channel 2 from a plurality of analog broadcast signals input from an antenna, generating a clock 2 by separating the synchronization signal of the channel 2, and converting the broadcast signal of the channel 2 into a digital signal and storing the same as the clock 2; ;
    Reading the stored digital signals according to the channel 1 and the channel 2 so as to correspond to the clock 3 and restoring them;
    Sequentially outputting the digital signals according to the restored channel 1 and channel 2 with a specific time difference;
    Selecting only a digital signal corresponding to a specific part of the digital signals corresponding to channel 1, selecting only a digital signal corresponding to a specific part of the digital signals corresponding to channel 2, and mixing the same into one video signal; And,
    Converting the mixed video signal into an analog signal, generating a sync signal, and outputting the sync signal to correspond to the generated sync signal.
    In addition, the split screen output control apparatus of the video reproducing apparatus according to an embodiment of the present invention for performing the second object,
    A plurality of tuners connected to output ends of the plurality of antennas to select a plurality of analog broadcast signals;
    A plurality of clock generation means connected to output terminals of the plurality of tuners, respectively, for generating first, second and third clocks so as to correspond to the synchronization signals of the input image signals;
    A plurality of A / D converters connected to output terminals of the plurality of tuners, respectively, to convert analog video signals into digital signals;
    A plurality of image signals converted to correspond to first and second clocks among a plurality of clocks outputted from the clock generation means, stored in a digital signal, and outputted from the clock generation means A plurality of line memories for outputting a digital video signal to correspond to a third clock of the clock;
    A plurality of field memories for storing the digital signals output from the plurality of line memories and sequentially outputting the stored digital signals;
    Output selection means connected to output terminals of the plurality of field memories, for selecting and outputting only a portion of the digital signals stored in the plurality of field memories, respectively;
    A D / A conversion unit connected to an output terminal of the output selection means for converting a digital video signal into an analog signal;
    A mixing device which is connected to an output terminal of the D / A converting unit and mixes a synchronization signal for outputting an analog video signal; And,
    A start signal having a specific time difference is sequentially applied to the plurality of field memories based on the first clock input from the plurality of clock generation means, and a selection signal is applied to the output selection means to select an output signal, and the synchronization is performed. And a control device for generating a signal and applying the signal to the mixing device.
    According to the present invention, it is possible to adjust the data output from the split screen without changing the aspect ratio in the image reproducing apparatus, and to prevent the distortion of the screen during the split screen output.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    3 is a block diagram illustrating an apparatus for controlling split screen output of an image reproducing apparatus according to an exemplary embodiment.
    As shown in FIG. 3, the split screen output control apparatus of the image reproducing apparatus according to the present invention includes a plurality of tuners 102a and 102b. The plurality of tuners 102a and 102b receive analog broadcast signals from antennas 100a and 100b connected to input terminals, respectively. A first sync signal separator 104a and a second sync signal separator 104b are connected to output terminals of the plurality of tuners 102a and 102b, respectively. The first sync signal separator 104a and the second sync signal separator 104b detect a sync signal from analog video signals input from the plurality of tuners 102a and 102b. A first PLL circuit 106a and a third PLL circuit 106c are connected to the output terminal of the first synchronization signal separator 104a. In addition, a second PLL circuit 106b is connected to the output terminal of the second synchronization signal separator 104b. The first PLL circuit 106a, the second PLL circuit 106b, and the third PLL circuit 106c receive a synchronization signal detected from an analog video signal, and the clock 1 and the clock required for storing the input video signal. Generate 2 and clock 3.
    The output terminals of the plurality of tuners 102a and 102b are connected to a first A / D converter 108a and a second A / D converter 108b for converting analog video signals into digital signals, respectively. The first line memory 110a and the second line memory 110b are connected to the output terminals of the first A / D converter 108a and the second A / D converter 108b, respectively. The first line memory 110a corresponds to the clock 1 and the clock 3 outputted from the first PLL circuit 106a and the third PLL circuit 106c by inputting an image signal input from an arbitrary channel 1 and digitally converted. Output it.
    In addition, the second line memory 110b transmits the image signals inputted from any channel 2 and converted into digital signals to the clock 1 and the clock 3 output from the second PLL circuit 106b and the third PLL circuit 106c. Save correspondingly.
    The first field memory 112a and the second field memory 112b are connected to the output terminals of the first line memory 110a and the second line memory 110b, respectively. The first field memory 112a and the second field memory 112b store the adjusted data in the first line memory 110a and the second line memory 110b.
    The MUX 114 is connected to the output terminals of the first field memory 112a and the second field memory 112b. The MUX 114 receives a digital signal output from the first field memory 112a and a digital signal output from the second field memory 112b, and selects and outputs a specific portion of each input digital signal.
    The output terminal of the MUX 114 is connected to a D / A converter 116 for converting a digital video signal into an analog signal. The mixing device 118 is connected to the output terminal of the D / A converter 116. The mixing device 118 mixes a synchronization signal indicating the start of the analog video signal output from the D / A converter 116.
    The clock 1 generated by the first PLL circuit 106a is input to the control device 120. The control device 120 receives the clock 1 generated by the first PLL circuit 106a and outputs an output signal to the first field memory 112a and the second field memory 112b based on the clock 1. A digital signal is output to apply the selection signal to the MUX 114 so as to select only a specific portion of the digital signals output from the first field memory 112a and the second field memory 112b. In addition, a pseudo synchronizing signal for notifying the start of the video signal is generated and applied to the mixing device 118.
    The detailed operation of the split screen output control apparatus of the video reproducing apparatus according to the embodiment of the present invention configured as described above is as follows.
    4A to 4D are schematic diagrams illustrating a split screen output from a split screen output control apparatus of an image reproducing apparatus according to each embodiment of the present invention.
    As shown in FIG. 4A to FIG. 4D, each embodiment of the present invention includes a first line memory 110a and a first PLL circuit 106a, a second PLL circuit 106b, and a third PLL circuit 106c. The division ratio of the screen is changed according to the frequencies of the clocks 1, 2, and 3 applied to the second line memory 110b. That is, as shown in FIG. 4A, when the screen of the image reproducing apparatus is vertically divided to output an image signal received in an arbitrary channel 1 and channel 2, the first line memory 110a and the second line memory. If the frequencies of clock 1, clock 2, and clock 3 applied to 110b are the same, as shown in FIG. 4B, only A and A 'portions of the channel 1 and the channel 2, that is, the center portion of the screen, are output without compression. In addition, if the frequencies of the clock 1 and the clock 2 are the same, and the frequency of the clock 3 is increased 1.5 times compared to the clock 1, as shown in FIG. The B and B 'part of 2 can be output.
    If the frequencies of clock 1 and clock 2 are the same, and the frequency of clock 3 is increased twice as much as that of clock 1, as shown in FIG. 4B, C and C 'portions of channels 1 and 2, which are the entire portions of the screen, are shown. Can be compressed and output in time.
    Example 1
    In the present embodiment, the first PLL circuit 106a, the second PLL circuit 106b, and the third PLL circuit 106c generate clock 1, clock 2, and clock 3 of the same frequency required for storing the video signal. Therefore, as shown in FIG. 4B, only the A and A 'portions of the channel 1 and the channel 2, that is, the center portion of the screen, are output without compression.
    5A to 5I are waveform diagrams for describing a split screen output process in the split screen output control apparatus of the image reproducing apparatus according to the present embodiment.
    3 and 5, the antennas 100a and 100b receive an analog broadcast signal transmitted from a broadcasting station. A plurality of tuners 102a and 102b receiving video signals of different channels are connected to the output terminals of the antennas 100a and 100b to output divided screens. In a typical split screen output method, a method of receiving a video signal of each channel from each tuner using two tuners and dividing the image into two equal parts is widely used. Subsequently, a detailed operation according to the present embodiment will be described based on a method of dividing the screen into two parts using two tuners and outputting a screen.
    The first and second tuners 102a and 102b separate signals of a set channel from a plurality of analog signals input through the antenna. If the video signal of channel 1 is separated through the first tuner 102a, and the video signal of channel 2 is separated through the second tuner 102b, the channel 1 separated through the first tuner 102a. The video signal of the channel 2 is input to the first sync signal separator 104a and the first A / D converter 108a, and the video signal of channel 2 separated through the second tuner 102b is a second sync signal separator ( 104b) and second A / D converter 108a.
    The first sync signal separator 104a separates the sync signal from the image signal of channel 1 and inputs it to the first PLL circuit 106a and the third PLL circuit 106c, and the second sync signal separator 104b. 를 separates the sync signal from the video signal of channel 2 and inputs it to the second PLL circuit 106b. The first PLL circuit 106a receives a synchronous signal separated from the image signal of channel 1 to generate a clock 1, and the second PLL circuit 106b receives a synchronous signal separated from the image signal of channel 2. Generate clock 2. In addition, the third PLL circuit 106c receives the synchronization signal separated from the image signal of the channel 1 to generate the clock 3.
    In Embodiment 1 of the present invention, the frequencies of clock 1, clock 2 and clock 3 are the same. The clock 1 and the clock 2 are respectively applied to the first line memory 110a and the second line memory 110b, and the clock 3 is simultaneously applied to the first line memory 110a and the second line memory 110b. do. The clock 1 and the clock 2 output the digital signals output from the first A / D converter 108a and the second A / D converter 108b to the first line memory 110a and the second line memory 110b. The clock 3 is used as a read clock for storing information stored in the first line memory 110a and the second line memory 110b.
    In addition, the analog video signal of channel 1 separated through the first tuner 102a is input to the first A / D converter 108a and converted into digital signals to be applied to the first line memory 110a. The analog video signal of channel 2 separated through the two tuners 102b is input to the second A / D converter 108b, converted into digital signals, and applied to the second line memory 110b.
    At this time, the first line memory 110a and the second line memory 110b receive the clock 1 and the clock 2, respectively, and the digital signal and the second A / D conversion inputted from the first A / D converter 108a. The digital signal input from the unit 108b is stored. Therefore, the digital signal corresponding to channel 1 is stored in the first line memory 110a as shown in FIG. 5A. In addition, the second line memory 110b stores a digital signal corresponding to channel 2 as shown in FIG. 5B.
    In this embodiment, since the clock 1, the clock 2, and the clock 3 are the same, the same digital signals as those shown in FIGS. 5A and 5B are output from the first line memory 110a and the second line memory 110b. . That is, since the clock 3 used as the read clock and the clock 1 and the clock 2 used as the write clock are the same, the same digital signal as the input digital signal is output. The digital signals output from the first line memory 110a and the second line memory 110b are stored in the first field memory 112a and the second field memory 112b.
    The control device 120 receives the clock 1 input from the first PLL circuit 106a and outputs a digital signal stored in the first field memory 112a and the second field memory 112b based on the clock 1. The first start signal and the second start signal are input.
    Referring to FIG. 5, the control device 120 receives the clock 1 and outputs the first start signal to the first field memory 112a as shown in FIG. 5H to output the digital signal corresponding to the channel 1 to the MUX 114. First). As shown in FIG. 5I, the digital signal corresponding to channel 2 is applied to the MUX 114 at the same time as 1/2 of the digital signal corresponding to channel 1 is outputted to the second field memory 112b. Output a second start signal.
    Therefore, when the digital signal a 'as shown in FIG. 5C in the first field memory 110a is input to the MUX 114, the signal a' and the second field memory 110b as shown in FIG. In the case of a specific time difference, that is, a two-split screen, a digital signal b 'having a parallax for outputting another signal in the middle portion where the image information of the signal a' is output is input to the MUX 114.
    When the signal a 'output from the first field memory 110a and the signal b' output from the second field memory 110b are input to the MUX 114, the control device 120 inputs the MUX 114 to FIG. 5F. As shown, a selection signal is applied to output a portion of the signals a 'and b'. That is, the controller 120 outputs a first start signal to the first field memory 112a so as to be synchronized with the clock 1, and a second start to the second field memory 112b at a half of the clock 1. Output the signal. Therefore, when 1/2 of the signal a 'is applied to the MUX 114, the time difference is adjusted so that the signal b' of the channel 2 is applied.
    As shown in FIG. 5E, the digital signal finally output from the MUX 114 outputs a digital signal in which image information of portion A of channel 1 and image information of portion A ′ of channel 2 are sequentially connected.
    In other words, when the control device 120 applies the high selection signal to the MUX 114 as shown in FIG. 5F, only the image information of the A portion of the center portion of the signal a output from the channel 1 is applied to the MUX 114. 114 is output to the D / A converter 116. In addition, when the control device 120 applies a low selection signal to the MUX 114, only the video information of the portion A ′ of the signal b output from the channel 2 is transmitted through the MUX 114. 116).
    The D / A converter 116 converts the analog video signal output from the MUX 114 to the mixing device 118 by converting an analog signal. The control device 120 receives the clock 1 generated by the first PLL circuit 106a, generates a pseudo synchronization signal as shown in FIG. 5G, and applies it to the mixing device 118. Accordingly, the analog video signal output from the D / A converter 116 corresponds to a cathode-ray tube (CRT) or a liquid crystal display (LCD) in response to the synchronization signal input from the control device 120. And AMA (Actuated Mirror Array; thin film type optical path adjusting device).
    Example 2
    In this embodiment, the first and second PLL circuits 106b output from the first and second PLL circuits 106a used to store digital signals in the first and second line memories 110a and 110b. The frequency of clock 2 to be set is the same. However, the clock 1 may be configured to generate a period of clock 3 required when the digital signal stored in the third PLL circuit 106c is used to store the digital signal in the first line memory 110a and the second line memory 110b. And 1.5 times as compared to clock 2. Therefore, as shown in FIG. 4C, a screen is output from the B and B 'portions of the channel 1 and the channel 2, that is, the portion extending from the center portion of the screen to the outside portion.
    6A to 6F are waveform diagrams for explaining the operation of the line memory in the split screen output control apparatus of the video reproducing apparatus according to the present embodiment.
    The detailed operation of the present invention will be described with reference to FIG. 3 or FIG. 5, analog broadcast signals transmitted from broadcasting stations, etc., are input through the antennas 100a and 100b, respectively, through different tuners 102a and 102b. It is separated into a video signal. In the present embodiment, a detailed operation will be described based on a method of outputting a screen divided into two portions using two tuners.
    The first and second tuners 102a and 102b separate signals of a set channel from a plurality of analog signals input through the antenna. If the video signal of channel 1 is separated through the first tuner 102a, and the video signal of channel 2 is separated through the second tuner 102b, the channel 1 separated through the first tuner 102a. The video signal of the channel 2 is input to the first sync signal separator 104a and the first A / D converter 108a, and the video signal of channel 2 separated through the second tuner 102b is a second sync signal separator ( 104b) and second A / D converter 108a.
    The first sync signal separator 104a separates the sync signal from the image signal of channel 1 and inputs it to the first PLL circuit 106a and the third PLL circuit 106c, and the second sync signal separator 104b. 를 separates the sync signal from the video signal of channel 2 and inputs it to the second PLL circuit 106b. The first PLL circuit 106a receives a synchronous signal separated from the image signal of channel 1 to generate a clock 1, and the second PLL circuit 106b receives a synchronous signal separated from the image signal of channel 2. Generate clock 2. In addition, the third PLL circuit 106c receives the synchronization signal separated from the image signal of the channel 1 to generate the clock 3.
    In this embodiment, as shown in FIG. 6A, the frequencies of clock 1 and clock 2 are the same. However, as shown in FIG. 6B, the period of clock 3 is increased by 1.5 times compared to clock 1 and clock 2. The clock 1 and the clock 2 are respectively applied to the first line memory 110a and the second line memory 110b, and the clock 3 is simultaneously applied to the first line memory 110a and the second line memory 110b. do. The clock 1 and the clock 2 output the digital signals output from the first A / D converter 108a and the second A / D converter 108b to the first line memory 110a and the second line memory 110b. The clock 3 is used as a read clock for storing information stored in the first line memory 110a and the second line memory 110b. The clock 1 and the clock 2 are used as a write clock used to store signals in the memory, and the clock 3 is used as a read clock used to read information stored in the memory.
    In addition, the analog video signal of channel 1 separated through the first tuner 102a is input to the first A / D converter 108a and converted into digital signals to be applied to the first line memory 110a. The analog video signal of channel 2 separated through the two tuners 102b is input to the second A / D converter 108b, converted into digital signals, and applied to the second line memory 110b.
    At this time, the first line memory 110a and the second line memory 110b receive the clock 1 and the clock 2, respectively, and the digital signal and the second A / D conversion inputted from the first A / D converter 108a. The digital signal input from the unit 108b is stored. Accordingly, a digital signal corresponding to channel 1 is stored in the first line memory 110a and a digital signal corresponding to channel 2 is stored in the second line memory 110b.
    In the present embodiment, clock 3 is used to read the digital signals stored in the first line memory 110a and the second line memory 110b. Clock 1 and clock 2, which are used as write clocks, are the same, and clock 3, which is used as read clocks, is a pulse of 1.5 times longer than the clock 1 and clock 2. Accordingly, as shown in FIG. 6D, the first line memory as shown in FIG. 6D is compared with the time required for storing N digital signals in the first line memory 110a and the second line memory 110b as shown in FIG. 6C. Time required for reading the N digital signals from 110a and the second line memory 110b is reduced by 1.5 times.
    As a result, when the digital signal shown in FIG. 6E is input to the first line memory 110a and the second line memory 110b, the input signal is compressed 1.5 times without loss of the signal as shown in FIG. 6F. do.
    The digital signals output from the first line memory 110a and the second line memory 110b are stored in the first field memory 112a and the second field memory 112b. The control device 120 receives the clock 1 input from the first PLL circuit 106a and outputs a digital signal stored in the first field memory 112a and the second field memory 112b based on the clock 1. The first start signal and the second start signal are input.
    Referring to FIG. 5, the control device 120 receives the clock 1 and outputs the first start signal to the first field memory 112a as shown in FIG. 5H to MUX the digital signal corresponding to the channel 1. Is first applied to (114). As shown in FIG. 5I, the digital signal corresponding to channel 2 is applied to the MUX 114 at the same time as 1/2 of the digital signal corresponding to channel 1 is outputted to the second field memory 112b. Output a second start signal.
    Therefore, when the digital signal a 'as shown in FIG. 5C in the first field memory 110a is input to the MUX 114, the signal a' and the second field memory 110b as shown in FIG. In the case of a specific parallax, that is, a two-split screen, a digital signal b 'having a parallax for outputting another signal in the middle portion where the image information of the signal a' is output is input to the MUX 114.
    When the signal a 'output from the first field memory 110a and the signal b' output from the second field memory 110b are input to the MUX 114, the control device 120 inputs the MUX 114 to FIG. 5F. As shown, a selection signal is applied to output a portion of the signals a 'and b'. That is, the controller 120 outputs a first start signal to the first field memory 112a so as to be synchronized with the clock 1, and a second start to the second field memory 112b at a half of the clock 1. Output the signal. Therefore, when 1/2 of the signal a 'is applied to the MUX 114, the time difference is adjusted so that the signal b' of the channel 2 is applied.
    As shown in FIG. 5E, the digital signal finally output from the MUX 114 outputs a digital signal in which image information of portion A of channel 1 and image information of portion A ′ of channel 2 are sequentially connected.
    In other words, when the control device 120 applies the high selection signal to the MUX 114 as shown in FIG. 5F, only the image information of the A portion of the center portion of the signal a output from the channel 1 is applied to the MUX 114. 114 is output to the D / A converter 116. In addition, when the control device 120 applies a low selection signal to the MUX 114, only the video information of the portion A ′ of the signal b output from the channel 2 is transmitted through the MUX 114. 116).
    The D / A converter 116 converts the analog video signal output from the MUX 114 to the mixing device 118 by converting an analog signal. The control device 120 receives the clock 1 generated by the first PLL circuit 106a, generates a pseudo synchronization signal as shown in FIG. 5G, and applies it to the mixing device 118. Accordingly, the analog video signal output from the D / A converter 116 corresponds to a cathode-ray tube (CRT) or a liquid crystal display (LCD) in response to a synchronization signal input from the control device 120. And AMA (Actuated Mirror Array; thin film type optical path adjusting device).
    Example 3
    In this embodiment, the first and second PLL circuits 106b output from the first and second PLL circuits 106a used to store digital signals in the first and second line memories 110a and 110b. The frequency of clock 2 to be set is the same. However, the clock 1 may be configured to generate a period of clock 3 required when the digital signal stored in the third PLL circuit 106c is used to store the digital signal in the first line memory 110a and the second line memory 110b. And twice as much as clock 2. Therefore, as shown in FIG. 4C, the C and C ′ portions of the channel 1 and the channel 2, that is, the entire screen are compressed and output.
    7A to 7F are waveform diagrams for explaining the operation of the line memory in the split screen output control apparatus of the video reproducing apparatus according to the present embodiment.
    The detailed operation of the present invention will be described with reference to FIG. 3 or FIG. 5, analog broadcast signals transmitted from broadcasting stations, etc., are input through the antennas 100a and 100b, respectively, through different tuners 102a and 102b. It is separated into a video signal. In the present embodiment, a detailed operation will be described based on a method of outputting a screen divided into two portions using two tuners.
    The first and second tuners 102a and 102b separate signals of a set channel from a plurality of analog signals input through the antenna. If the video signal of channel 1 is separated through the first tuner 102a, and the video signal of channel 2 is separated through the second tuner 102b, the channel 1 separated through the first tuner 102a. The video signal of the channel 2 is input to the first sync signal separator 104a and the first A / D converter 108a, and the video signal of channel 2 separated through the second tuner 102b is a second sync signal separator ( 104b) and second A / D converter 108a.
    The first sync signal separator 104a separates the sync signal from the image signal of channel 1 and inputs it to the first PLL circuit 106a and the third PLL circuit 106c, and the second sync signal separator 104b. 를 separates the sync signal from the video signal of channel 2 and inputs it to the second PLL circuit 106b. The first PLL circuit 106a receives a synchronous signal separated from the image signal of channel 1 to generate a clock 1, and the second PLL circuit 106b receives a synchronous signal separated from the image signal of channel 2. Generate clock 2. In addition, the third PLL circuit 106c receives the synchronization signal separated from the image signal of the channel 1 to generate the clock 3.
    In this embodiment, as shown in FIG. 7A, the frequencies of clock 1 and clock 2 are the same. However, as shown in FIG. 7B, the period of clock 3 is doubled compared to clock 1 and clock 2. The clock 1 and the clock 2 are respectively applied to the first line memory 110a and the second line memory 110b, and the clock 3 is simultaneously applied to the first line memory 110a and the second line memory 110b. do. The clock 1 and the clock 2 output the digital signals output from the first A / D converter 108a and the second A / D converter 108b to the first line memory 110a and the second line memory 110b. The clock 3 is used as a read clock for storing information stored in the first line memory 110a and the second line memory 110b. The clock 1 and the clock 2 are used as a write clock used to store signals in the memory, and the clock 3 is used as a read clock used to read information stored in the memory.
    In addition, the analog video signal of channel 1 separated through the first tuner 102a is input to the first A / D converter 108a and converted into digital signals to be applied to the first line memory 110a. The analog video signal of channel 2 separated through the two tuners 102b is input to the second A / D converter 108b, converted into digital signals, and applied to the second line memory 110b.
    At this time, the first line memory 110a and the second line memory 110b receive the clock 1 and the clock 2, respectively, and the digital signal and the second A / D conversion inputted from the first A / D converter 108a. The digital signal input from the unit 108b is stored. Accordingly, a digital signal corresponding to channel 1 is stored in the first line memory 110a, and a digital signal corresponding to channel 2 is stored in the second line memory 110b.
    In the present embodiment, clock 3 is used to read the digital signals stored in the first line memory 110a and the second line memory 110b. Clock 1 and clock 2, which are used as write clocks, are the same, and clock 3, which is used as read clocks, is a pulse of which the period is increased twice as compared to the clocks 1 and 2. Therefore, as shown in FIG. 7D, the first line memory as shown in FIG. 7D is compared with the time required for storing N digital signals in the first line memory 110a and the second line memory 110b as shown in FIG. 7C. The time required to read the N digital signals at 110a and the second line memory 110b is reduced by twice.
    As a result, when the digital signal as shown in FIG. 7E is input to the first line memory 110a and the second line memory 110b, the input signal is compressed and output twice without loss as shown in FIG. 7F. do.
    The digital signals output from the first line memory 110a and the second line memory 110b are stored in the first field memory 112a and the second field memory 112b. The control device 120 receives the clock 1 input from the first PLL circuit 106a and outputs a digital signal stored in the first field memory 112a and the second field memory 112b based on the clock 1. The first start signal and the second start signal are input.
    Referring to FIG. 5, the control device 120 receives the clock 1 and outputs the first start signal to the first field memory 112a as shown in FIG. 5H to MUX the digital signal corresponding to the channel 1. Is first applied to (114). As shown in FIG. 5I, the digital signal corresponding to channel 2 is applied to the MUX 114 at the same time as 1/2 of the digital signal corresponding to channel 1 is outputted to the second field memory 112b. Output a second start signal.
    Therefore, when the digital signal a 'as shown in FIG. 5C in the first field memory 110a is input to the MUX 114, the signal a' and the second field memory 110b as shown in FIG. In the case of a specific parallax, that is, a two-split screen, a digital signal b 'having a parallax for outputting another signal in the middle portion where the image information of the signal a' is output is input to the MUX 114.
    When the signal a 'output from the first field memory 110a and the signal b' output from the second field memory 110b are input to the MUX 114, the control device 120 inputs the MUX 114 to FIG. 5F. As shown, a selection signal is applied to output a portion of the signals a 'and b'. That is, the controller 120 outputs a first start signal to the first field memory 112a so as to be synchronized with the clock 1, and a second start to the second field memory 112b at a half of the clock 1. Output the signal. Therefore, when 1/2 of the signal a 'is applied to the MUX 114, the time difference is adjusted so that the signal b' of the channel 2 is applied.
    As shown in FIG. 5E, the digital signal finally output from the MUX 114 outputs a digital signal in which image information of portion A of channel 1 and image information of portion A ′ of channel 2 are sequentially connected.
    In other words, when the control device 120 applies the high selection signal to the MUX 114 as shown in FIG. 5F, only the image information of the A portion of the center portion of the signal a output from the channel 1 is applied to the MUX 114. 114 is output to the D / A converter 116. In addition, when the control device 120 applies a low selection signal to the MUX 114, only the video information of the portion A ′ of the signal b output from the channel 2 is transmitted through the MUX 114. 116).
    The D / A converter 116 converts the analog video signal output from the MUX 114 to the mixing device 118 by converting an analog signal. The control device 120 receives the clock 1 generated by the first PLL circuit 106a, generates a pseudo synchronization signal as shown in FIG. 5G, and applies it to the mixing device 118. Accordingly, the analog video signal output from the D / A converter 116 corresponds to a cathode-ray tube (CRT) or a liquid crystal display (LCD) in response to a synchronization signal input from the control device 120. And AMA (Actuated Mirror Array; thin film type optical path adjusting device).
    Therefore, a part of the video signal input from each channel is output to the split screen of the video reproducing apparatus, thereby preventing the screen from being distorted.
    As described above, in the split screen output control method of the image reproducing apparatus and the apparatus for performing the same, the amount of the image signal output on the screen is adjusted by adjusting the period of the clock applied to the memory. Only a specific portion of the video signal input from each channel is output on the screen to reduce the distortion of the screen.
    Although the present invention has been described in detail with reference to the accompanying drawings, the present invention is not limited thereto, and modifications and improvements are possible without departing from the ordinary knowledge of those skilled in the art. Particularly, in the exemplary embodiment of the present invention, only the screen output control method and apparatus in the divided state are presented, but it is obvious that the divided screen output control is possible even in the multi-division of two or more divisions according to the above technical concept.
    权利要求:
    Claims (14)
    [1" claim-type="Currently amended] I) Selecting channel 1 of a plurality of analog broadcast signals input from the antenna, and separating the synchronization signal of the channel 1 to generate a clock 1 and a clock 3 having a different frequency from the clock 1, and the broadcast signal of the channel 1 Converting to digital and storing corresponding to clock 1;
    Ⅱ) Selecting channel 2 among a plurality of analog broadcast signals input from an antenna, generating a clock 2 by separating the synchronization signal of the channel 2, and converting the broadcast signal of the channel 2 into a digital signal and storing the clock 2 correspondingly. Making a step;
    III) reading the stored digital signals according to the channel 1 and the channel 2 so as to correspond to the clock 3 and restoring them;
    IV) sequentially outputting the digital signals according to the restored channel 1 and channel 2 with a specific time difference;
    V) selecting only digital signals corresponding to a specific portion of the digital signals corresponding to the channel 1, selecting only digital signals corresponding to a specific portion of the digital signals corresponding to the channel 2, and mixing them into one image signal; And,
    VI) converting the mixed video signal into an analog signal, generating a sync signal, and outputting the sync signal according to the generated sync signal.
    [2" claim-type="Currently amended] The method of claim 1, wherein the step I is to generate clocks 1 and 2 having the same frequency.
    [3" claim-type="Currently amended] The method of claim 1, wherein the step (I) is a step of generating a clock 3 having a period 1.5 times increased with respect to the clock 1 and the clock 2.
    [4" claim-type="Currently amended] The method of claim 1, wherein the step (I) is a step of generating a clock 3 having a doubled period with respect to the clock 1 and the clock 2.
    [5" claim-type="Currently amended] The divided screen of the image reproducing apparatus according to claim 1, wherein the step (IV) is a step of outputting a digital signal corresponding to channel 2 at a time point at which 1/2 part of the stored digital signals corresponding to channel 1 is output. Output control method.
    [6" claim-type="Currently amended] The method of claim 1, wherein step V does not output a portion corresponding to an initial quarter of the digital signals corresponding to channel 1, and outputs only a digital signal of a portion corresponding to the next 2/4, And outputting a digital signal of a part corresponding to the / 4.
    [7" claim-type="Currently amended] The method of claim 1, wherein step V does not output a portion corresponding to an initial quarter of the digital signals corresponding to channel 2, and outputs only a digital signal corresponding to 2/4 of an intermediate portion. And a step of not outputting a digital signal corresponding to a quarter of the quadrature.
    [8" claim-type="Currently amended] A plurality of tuners 102a and 102b connected to output ends of the plurality of antennas 100a and 100b to select a plurality of analog broadcast signals;
    A plurality of clock generating means connected to output terminals of the plurality of tuners (102a, 102b) to generate first, second and third clocks so as to correspond to the synchronization signals of the input image signals;
    A plurality of A / D converters 108a and 108b connected to output terminals of the plurality of tuners 102a and 102b, respectively, to convert analog video signals into digital signals;
    Connected to the output terminals of the plurality of A / D converters 108a and 108b to store digitally converted image signals to correspond to first and second clocks among the plurality of clocks output from the clock generation means, and the clock A plurality of line memories (110a, 110b) for outputting a digital image signal to correspond to a third clock of the plurality of clocks output from the generating means;
    A plurality of field memories 112a and 112b for storing the digital signals output from the plurality of line memories 110a and 110b and sequentially outputting the stored digital signals;
    Output selecting means (114) connected to the output terminals of the plurality of field memories (112a, 112b) for selecting and outputting only a part of the digital signals stored in the plurality of field memories (112a, 112b), respectively;
    A D / A converter 116 connected to an output terminal of the output selector 114 for converting a digital video signal into an analog signal;
    A mixing device (118) for mixing a synchronization signal connected to an output terminal of the D / A converter (116) to output an analog video signal; And,
    On the basis of the first clock input from the plurality of clock generating means, a start signal having a specific time difference is sequentially applied to the plurality of field memories 112a and 112b, and a selection signal is applied to the output selecting means to output an output signal. And a control device (120) for generating a synchronization signal and applying it to the mixing device (118).
    [9" claim-type="Currently amended] 9. The apparatus of claim 8, wherein the clock generating means is connected to output terminals of the plurality of tuners 102a and 102b, respectively, and connected to an output terminal of a plurality of sync signal separators and a sync signal separator for detecting a sync signal from an analog video signal. And a PLL circuit for generating a clock so as to store an input video signal.
    [10" claim-type="Currently amended] 10. The apparatus of claim 9, wherein a plurality of PLL circuits are connected to an output terminal of any one of the plurality of tuners 102a and 102b connected to the clock generating means to output pulses having different periods. A split screen output control device of a video reproducing apparatus.
    [11" claim-type="Currently amended] The method of claim 8, wherein the first start signal output from the control device 120 is output to correspond to a clock input to the control device, and the second start signal is a signal output from 1/2 of the clock. A split screen output control apparatus of a video reproducing apparatus.
    [12" claim-type="Currently amended] The apparatus of claim 8, wherein the first clock and the second clock generated by the clock generating means have the same frequency.
    [13" claim-type="Currently amended] The apparatus of claim 8, wherein the third clock generated by the clock generating means is a frequency of 1.5 times longer than the first and second clocks.
    [14" claim-type="Currently amended] The apparatus of claim 8, wherein the third clock generated by the clock generating means is a frequency of which the period is increased by two times compared to the first and second clocks.
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    同族专利:
    公开号 | 公开日
    KR100225581B1|1999-10-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-27|Application filed by 배순훈, 대우전자 주식회사
    1996-12-27|Priority to KR1019960074013A
    1998-09-25|Publication of KR19980054828A
    1999-10-15|Application granted
    1999-10-15|Publication of KR100225581B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960074013A|KR100225581B1|1996-12-27|1996-12-27|Method for a picture in picture output controlling and an apparatus for performing the same|
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